1. Field
Embodiments of the present invention relates generally to a semiconductor design technology and, more particularly, to a semiconductor memory device that is suitable for performing a repair operation.
2. Description of the Related Art
Semiconductor memory devices include a plurality of memory banks for storing data, and each of the memory banks includes more than tens of millions of memory cells. Each of the memory cells may include a capacitor for storing data in the form of a charge and a transistor for controlling the charging and discharging of the capacitor. Semiconductor memory devices store data in memory cells through the operations of charging or discharging the capacitors of the memory cells. Theoretically, cell capacitors maintain a constant amount of charges stored therein if there is no other voltage or current applied thereto. However, in actuality, the amount of charges stored in cell capacitors may change due to a voltage difference with a peripheral circuit. Such a voltage difference may cause charges to leak out of charged cell capacitors, or may make more charges to enter into the cell capacitors. A substantial change in the amount of charges in cell capacitors may signify that the data stored in the cell capacitors is changed, which means that the data stored in the cell capacitors is lost.
To prevent stored data from being lost, semiconductor memory devices perform a refresh operation.
As fabrication technology advances, the integration degree of semiconductor memory devices is Increasing more and more, which increases the number of memory cells to be refreshed as well. Therefore, a refresh operation is to be periodically performed on a plurality of memory cells at once. In a semiconductor memory device, a refresh operation is performed on a basis of memory blocks. A refresh operation may be performed simultaneously on a plurality of memory blocks, or may be performed on the memory blocks in a sequential manner with a predetermined temporal interval between each memory block refresh for reducing instant current consumption.
For example, when a refresh operation is performed in parallel on a plurality of memory cell array regions inside a semiconductor memory device, the refresh operation may be performed by dividing the memory cell array regions on a basis of memory blocks. In this case, since the refresh operation is to be performed on all the memory blocks in parallel, block selection signals for enabling the corresponding memory blocks may be enabled concurrently, or enabled with a slight temporal interval between them. Therefore, since the refresh operations performed on the memory blocks in parallel overlap each other, all the memory blocks may be enabled at the same time.
A memory block, which is a unit for a refresh operation, is divided into a normal cell region and a redundant cell region. The normal cell region may include memory cells for storing data and the redundant cell region may include memory cells for repairing defective cells of the normal cell region. An operation for repairing defective cells of the normal cell region is called a repair operation. When a refresh operation is performed on a defective cell, a redundant cell used for repairing the defective cell is to be refreshed. Thus, when the addresses of target memory cells to be refreshed for each memory block are inputted, it is decided whether the target memory cells are in the redundant cell region or in the normal cell region, and then the refresh operation is performed on the target memory cells of the corresponding regions.
Typically, a repair operation for defective memory cells includes a repair operation performed on the stage of wafer and a repair operation performed on the stage of package. The repair operation performed on the stage of package is called a post-package repair (PPR) operation.
A soft PPR (SPPR) mode, which is a kind of a PPR operation, stores an external repair address information in a register or a latch. In an SPPR mode, a predetermined address is stored in the register or the latch, and when the stored address is the same as the address received during an operation of a semiconductor memory device, an SPPR enable signal for accessing a redundant memory cell may be generated.
Therefore, the memory blocks on which a refresh operation is performed may be controlled by using the block selection signals in such a manner that the memory blocks share an SPPR enable signal and only a predetermined memory block may access the redundant cell region. When a block selection signal is enabled while the SPPR enable signal is enabled, the redundant cell region of a memory block corresponding to the block selection signal may be accessed.
As described above, refresh operations performed on memory blocks in parallel may overlap each other, and in the SPPR mode, the memory blocks may be controlled by sharing the SPPR enable signal. Therefore, among a plurality of memory blocks, a refresh operation may be properly performed on a memory block with a target address in the SPPR mode by selecting the redundant cell region thereof. However, the refresh operation may not be properly performed for the other memory blocks, since the memory blocks share the SPPR enable signal, and the normal cell region thereof is not selected.